1) Field of the Invention
This invention pertains to inventive methods of manufacturing a semiconductor device for improving device performance, and to the resulting unique high-performance device structure. In particular, this invention has improved charge mobility in FET devices by structurally imposing tensile and compression forces in a device substrate during device fabrication.
2) Description of the Prior Art
One of the main challenges of deep submicron transistor design is to improve its carrier mobility, so that its drive current is higher and resulted in higher ring oscillator speed. It is known that tensile stress favor electron's mobility, while compressive stress favor hole's mobility.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following.
U.S. Pat. No. 6,825,529 and Ser. No. US 20040113217A1 Stress inducing spacers—Spacer structure for semiconductor devices formed in substrate, has two spacer structures, each comprising stress inducing material adjacent to both sidewall of one of device's gate terminal and its channel which applies mechanical stress—Inventor: Chidambarrao
U.S. Pat. No. 6,512,273: Method and structure for improving hot carrier immunity for devices with very shallow junctions—Complementary metal oxide semiconductor field effect transistor includes silicon nitride and polysilicon spacers provided on edge surface gate of p-channel and n-channel devices=Inventor: Krivokapic, Zoran
U.S. Pat. No. 6,573,172: Methods for improving carrier mobility of PMOS and NMOS devices—Fabrication of semiconductor device by forming P-channel and N-channel metal oxide semiconductor transistors in wafer, forming tensile film on P-channel transistor and forming compressive film on N-channel transistor—Inventor: En, et al.
Ser. No. US20040191975 A1: Nitrogen Controlled Growth Of Dislocation Loop In Stress Enhanced Transistor—MOSFET fabricating method, involves implanting silicon in substrate to form dislocation loop in substrate below conduction channel, and doping substrate with nitrogen below conduction channel—Inventor: Weber et al.
Ser. No. US20040104405A1: Novel CMOS device—Improving mobility of holes and electrons within semiconductor device structure, involves forming first and second stress layers over p- and n-type metal oxide semiconductor device respectively—Inventor: Huang
Ser. No. US20030040158A1: Semiconductor device and method of fabricating the same—Semiconductor device includes first nitride layer containing tensile stress and second nitride layer containing compressive stress—Inventor: Saitoh, Takehiro
U.S. Pat. No. 20040262784 High performance CMOS device structures and method of manufacture—A semiconductor device structure includes at least two field effect transistors formed on same substrate, the first field effect transistor includes a spacer having a first width, the second field effect transistor includes a compressive spacer having a second width, the first width being different than said second width. Preferably, the first width is narrower than the second width. A tensile stress dielectric film forms a barrier etch stop layer over the transistors. Inventors: Bruce B. Doris, Dureseti Chidambarrao, Suk Hoon Ku
U.S. Pat. No. 4,966,663: Method for forming a silicon membrane with controlled stress—Silicon membrane with predetermined stress characteristics—made by doping and electrochemical etching. Inventor: Mauger, Philip E.; Santa—A method for fabricating a silicon membrane with predetermined stress characteristics. A silicon substrate is doped to create a doped layer as thick as the desired thickness of the membrane. Stress within the doped layer is controlled by selecting the dopant based on its atomic diameter relative to silicon and controlling both the total concentration and concentration profile of the dopant. The membrane is then formed by electrochemically etching away the substrate beneath the doped layer.